In a symmetric multi-processor (SMP) system, a number of processors are connected together by means of a system bus. The system bus may be used by only one processor at a time. Other devices, such as storage and I/O devices, are also connected to the system bus. These devices, and other system resources, such as clocks, timers, direct memory access, and memory refresh controls, are shared by the processors.
During system reset, sometimes referred to as power-on-reset (POR), one of the processors is designated as the master processor. The master processor typically takes control of the system bus, and then initializes each of the other processors. The master processor also initializes the other devices in the system, and coordinates the starting of the entire system. For example, the master processor may test various parts of the system, such as memory areas. After system initialization, the master processor may designate a different processor as the master processor, or may remain the master processor. During operation of the system, the master processor may assign work to the other processors.
When a system is powered on, one of the processors is designated as the master processor. Prior art methods for determining which processor is to be the master processor are typically hardware-based methods, which can not be changed or controlled without making a hardware change. For example, in "Method to Determine a Lead Processor in a Symmetric Multi-Processor System," IBM Technical Disclosure Bulletin, Vol. 39, No. 05, May 1996, pp. 53-54, each processor has an equal chance to become the master. A system bus arbiter determines which processor is granted access to the bus in order to read a first access register. Thus, the master selection process can not be controlled or changed without changing the hardware.
Another prior art method, "Start-Up Master Processor Selection Method For Multi-Processor Systems," IBM Technical Disclosure Bulletin, Vol. 33, No. 4, September 1990, pp. 375-376, discloses a method based on start-up circuitry in a system resource unit. The start-up circuitry polls each processor sequentially in order to find the first processor capable of becoming the master. The master processor then informs the other processor units that they are slave processors. The master processor selection can only be controlled by changing the hardware wiring, as the master processor is always the first processor to be polled. Further, this method may not always result in a successful system initialization. If one of the processing units malfunctions, and fails to stop driving the Ready line, the start-up circuitry will never start, and the system will not come up.
Consequently, there is a need for a system and method for determining which processor is to be the master processor in an SMP environment. It would be desirable for the system and method to be controllable and changeable, without the need for any special or dedicated hardware. It would also be desirable to increase the probability that the system will always successfully select a master processor, and will initialize successfully even if one or more of the processors malfunctions.